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hi-3182, hi-3183, hi-3184 hi-3185, hi-3186, hi-3188 the hi-3182, hi-3183, hi-3184, hi-3185, hi-3186 and hi-3188 bus interface products are silicon gate cmos devices designed as a line driver in accordance with the arinc 429 bus specifica- tions. in addition to being functional upgrades of holt's hi-8382 & hi-8383 products, they are also alternate sources for the hs-3182 ( intersil/harris), the rm3182 (fairchild /raytheon) and a variety of similar line driver products from other manufac- turers. inputs are provided for clocking and synchronization. these signals are and'd with the data inputs to enhance system performance and allow the hi-318x series of products to be used in a variety of applications. both logic and synchronization inputs feature built-in 2,000v minimum esd input protection as well as ttl and cmos compatibility. the differential outputs of the hi-318x series of products are programmable to either the high speed or low speed arinc 429 output rise and fall time specifications through the use of two external capacitors. the output voltage swing is also adjustable by the application of an external voltage to the vref input. products with 0, 13 or 37.5 ohm resistors in series with each arinc output are available. in addition, the fuse in series with each output. the hi-318x series of line drivers are intended for use where logic signals must be converted to arinc 429 levels such as when using an asic, the hi-3282/hi-8282a arinc 429 serial transmitter/dual receiver, the hi-6010 arinc 429 transmit- ter/receiver or the hi-8783 arinc interface device. holt products are readily available for both industrial and military applications. please contact the holt sales department for additional information. hi-3182 and hi-3184 products also have a pin configuration (top view) general description low power cmos ttl and cmos compatible inputs programmable output voltage swing plastic 14 & 16-pin thermally enhanced soic packages available pin-for-pin alternative for intersil/fairchild applications operates at data rates up to 100 kbits overvoltage protection industrial and extended temperature ranges adjustable arinc rise and fall times features hi-3184ps, hi-3185ps & hi-3186ps 14 - pin plastic small outline (esoic) nb ** function arinc 429 differential line driver _ + truth table march 2008 arinc 429 differential line driver 14 v 13 clock 12 data (b) 11 c 10 b 9+v 8 gnd 1 b out v1 gnd (see note * ) 2 sync 3 data (a) 4 c5 a6 -v 7 ref a out (see page 6 for additional package pin configurations) notes: * pin 2 may be left floating ** thermally enhanced soic package (ds3182 rev. k ) 03/09 sync clock data(a) data(b) aout bout comments x l x x 0v 0v null l x x x 0v 0v null h h l l 0v 0v null h h l h -v +v low h h h l +v -v high h h h h 0v 0v null ref ref ref ref holt integrated circuits www.holtic.com
functional description the sync and clock inputs establish data synchronization utilizing two and gates, one for each data input (figure 2). each logic input, including the power enable ( ) input, are ttl/cmos compatible. figure 1 illustrates a typical arinc 429 bus application. three power supplies are necessary to operate the hi-3182; typically +15v, -15v and +5v. the chip also works with 12v supplies. the +5v supply can also provide a reference voltage that determines the output voltage swing. the differential output voltage swing will equal 2v . if a value of v other than +5v is needed, a separate +5v power supply is required for pin v . with the data (a) input at a logic high and data (b) input at a logic low, a will switch to the +v rail and b will switch to the -v rail (arinc high state). with both data input signals at a logic low state, the outputs will both switch to 0v (arinc null state). the driver output impedance, r , is nominally 75, 26 or 0 ohms depending on the option chosen. the rise and fall times of the outputs can be calibrated through the selection of two external capacitor values th re connected to the c and c input pins. typical values for high-speed operation (100kbps) are c = c = 75pf and for low-speed operation (12.5 to 14kbps) c = c = 500pf. strobe ref ref out ref out ref out 1 ab ab ab at a the c and c pins swing between +5v and ground allowing the switching of capacitor values with an external single- supply analog switch. ab the arinc outputs can be put in a tri-state mode by applying a logic high to the input pin. if this feature is not being used, the pin should be tied to ground. the strobe strobe function is not available in the 14 & 16-pin soic package configurations where the pin is internally connected to ground. the arinc outputs of the hi-3182 and hi-3184 are protected by internal fuses capable of sinking between 800 - 900 ma for short periods of time (125 s). the vref pin has an internal pull-up resistor to v+, allowing the use of a simple external zener diode to set the reference voltage. power supply sequencing the power supplies should be controlled to prevent large currents during supply turn-on and turn-off. the recommended sequence is +v followed by v , always ensuring that +v is the most positive supply. the -v supply is not critical and can be asserted at any time. 1 hi-3182, hi-3183, hi-3184, hi-3185, hi-3186, hi-3188 data (a) out data (b) inputs to arinc bus a out b ref v 1 v sync clock -v +v strobe gnd b a c c -15v +15v +5v figure 1. arinc 429 bus application figure 2. functional block diagram out b shorted on hi-3186, hi-3188 c l ref f a r l f b out a output driver (b) output driver (a) b c gnd -v data (a) data (b) sync clock v 1 strobe a c v +v level shifter and slope control (b) level shifter and slope control (a) current regulator 13 13 24.5 shorted on hi-3183, hi-3186 hi-3188 shorted on hi-3183, hi-3185 hi-3186, hi-3188 24.5 holt integrated circuits 2
note: stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. parameter symbol conditions operating range maximum unit differential voltage v voltage between +v and -v terminals 40 v supply voltage +v +10.8 to +16.5 v -v -10.8 to -16.5 v v +5 5% +7 v voltage reference v for arinc 429 +5 5% 6 v for applications other than arinc 1.5 to 6 6 v input voltage range v gnd -0.3 v v1 +0.3 v output short-circuit duration see note: 1 output overvoltage protection see note: 2 operating temperature range t industrial -40 to +85 c extended -55 to +125 c storage temperature range t ceramic & plastic -65 to +150 c lead temperature soldering, 10 seconds +275 c junction temperature t +175 c note 1. heatsinking may be required for continuous output short circuit at +125c and for 100kbps at +125c. note 2. the fuses used for output overvoltage protection may be blown by the presence of a voltage at either output that is greater than 12.0v with respect to gnd. (hi-3182 & 3184 only) dif 1 ref in a stg j > < all voltages referenced to gnd, ta = operating temperature range (unless otherwise specified) absolute maximum ratings symbol function description v analog ref. voltage used to determine output voltage swing. pin sources current to allow use of a zener reference. input a logic high tri-states the arinc outputs. not available in the 14-pin soic package (tied to gnd internally). sync input synchronizes data inputs data (a) input data input terminal a c input connection for data (a) slew-rate capacitor a output arinc output terminal a -v power -12v to -15v gnd power 0.0v +v power +12v to +15v b output b c input data (b) input b clock input synchronizes data inputs v power +5v 5% ref a out out b 1 strobe arinc output terminal connection for data (b) slew-rate capacitor data input terminal pin descriptions hi-3182, hi-3183, hi-3184, hi-3185, hi-3186, hi-3188 holt integrated circuits 3
figure 3. switching waveforms -9.5v to -10.5v +9.5v to +10.5v -4.75v to -5.25v 2.0v +4.75v to +5.25v 2.0v 0.5v 0.5v -4.75v to -5.25v +4.75v to +5.25v data (a) 0v data (b) 0v a out 0v b out 0v differential output 0v () ab out - out 50% 50% v ref adjust by c a t phl adjust by c a -v ref 50% 50% t plh t r +v ref -v ref adjust by c b adjust by c b t f 2v ref -2v ref high null low note: outputs unloaded parameter symbol condition min typ max units rise time ( , ) = = 75pf see figure 3. 1.0 2.0 s fall time ( , ) = = 75pf see figure 3. 1.0 2.0 s propagtion delay input to output = = 75pf see figure 3. 3.0 s propagtion delay input to output = = 75pf see figure 3. 3.0 s ab t cc ab t cc tcc tcc out out r a b out out f a b plh a b phl a b +v = +15v, -v = -15v, v = v = +5.0v, t = operating temperature range (unless otherwise specified). 1 ref a ac electrical characteristics parameter symbol condition min typ max units supply current +v (operating) (+v) no load (0 - 100kbps) +16 ma supply current -v (operating) (-v) no load (0 - 100kbps) -16 ma supply current (operating) ( ) no load (0 - 100kbps) 500 a reference pin current (operating) ( ) no load, ref = 5v (0 - 100kbps) -1.0 -0.4 -0.15 ma supply current +v (during short circuit test) (+v) short to ground (see note: 1) 150 ma supply current -v (during short circuit test) (-v) short to ground (see note: 1) -150 ma output short circuit current (output high) short to ground =0 (see note: 2) -80 ma output short circuit current (output low) short to ground =0 (see note: 2) +80 ma input current (input high) 1.0 a input current (input low) -1.0 a input voltage high 2.0 v input voltage low 0.5 v output voltage high (output to ground) no load (0 -100kbps) +v +v v -. +. output voltage low (output to ground) no load (0 -100kbps) -v -v v -. +. output voltage null no load (0-100kbps) -250 +250 mv input capacitance 15 pf i i viv vivv i i iv iv i i v v v v v c ccop ccop 1 ccop 1 ref ccop ref sc sc ohsc min olsc min ih il ih il oh 25 25 ol 25 25 null in see note 1 ref ref ref ref note 1. not tested, but characterized at initial device design and after major process and/or design change which affects this parameter. note 2. interchangeability of force and sense is acceptable. +v = +15v, -v = -15v, v = v = +5.0v, t = operating temperature range (unless otherwise specified). 1 ref a dc electrical characteristics hi-3182, hi-3183, hi-3184, hi-3185, hi-3186, hi-3188 holt integrated circuits 4
dissipation. the heat sink is electrically isolated from the chip and can be soldered to any ground or power plane. however, since the chip?s substrate is at +v, connecting the heat sink to this power plane is recommended to avoid coupling noise into the circuit. heat sink - esoic packages both the 14-pin and 16-pin thermally enhanced soic packages are used for hi-318x products. these esoic packages include a metal heat sink located on the bottom surface of the device. this heat sink should be soldered down to the printed circuit board for optimum thermal notes: 1. all data taken on devices soldered to a single layer copper pcb (3" x 4.5" x .062"). 2. at 100% duty cycle, 15v power supplies. for 12v power supplies multiply all tabulated values by 0.8. 3. high speed: data rate = 100 kbps, load : r = 400 ohms ,c=10nf. data not presented fo rc=30nf as this is considered unrealistic for high speed operation. 4. similar results would be obtained with a shorted to b . 5. for applications requiring survival with continuous short circuit, operation above tj = 175c is not recommended. 6. data will vary depending on air flow and the method of heat sinking employed. 7. current values listed are for each of the +v and -v supplies. in still air out out ?ja junction temperature, tj package style heat sink supply current (c/w) ta = 25c ta = 85c ta = 125c 14-pin thermally enhanced plastic soic (esoic) 1 2 unsoldered 82 36 ma 57c 147c 187c soldered 65 36 ma 78c 138c 178c unsoldered 51 40 ma 64c 124c 164c soldered 28 40 ma 53c 113c 153c n/a 70 63 ma 100c 150c 182c 14-pin thermally enhanced plastic soic (esoic) 28-pin plastic a and b shorted to ground out out 3, 4, 5, 6, 7 ?ja junction temperature, tj package style heat sink supply current (c/w) ta = 25c ta = 85c ta = 125c 14-pin thermally enhanced plastic soic (esoic) 1 2 unsoldered 82 20 ma 57c 117c 157c soldered 65 20 ma 51c 111c 151c unsoldered 51 20 ma 45c 105c 145c soldered 28 20 ma 36c 96c 136c n/a 70 25 ma 56c 110c 150c 14-pin thermally enhanced plastic soic (esoic) 28-pin plastic maximum arinc load 3, 6, 7 hi-318x package thermal characteristics hi-3182, hi-3183, hi-3184, hi-3185, hi-3186, hi-3188 holt integrated circuits 5
additional pin configurations (see page 1 for 14-pin small outline soic) vref strobe sync data(a) ca aout -v gnd +v n/c bout cb data(b) clock v1 n/c 1 2 3 4 5 6 7 89 10 11 12 13 14 15 16 hi-3182cd hi-3183cd 16 - pin ceramic side brazed dip v-1 gnd (see note * ) - 2 sync - 3 data(a) - 4 c-5 a-6 -v - 7 gnd - 8 ref a out 16 - v 15 - n/c 14 - clock 13 - data(b) 12 - c 11 - b 10 - n/c 9-+v 1 b out hi-3182ps, hi-3183ps, hi-3188ps notes: ** thermally enhanced soic package * pin 2 may be left floating hi-3182, hi-3183, hi-3184, hi-3185, hi-3186, hi-3188 vref strobe sync data(a) ca aout -v gnd +v n/c bout cb data(b) clock v1 n/c 1 2 3 4 5 6 7 89 10 11 12 13 14 15 16 hi-3182cr hi-3183cr 16 - pin cerdip 56 78910111213 30 31 32 1 2 3 4 20 19 18 17 16 15 14 n/c n/c +v gnd n/c -v n/c clock v n/c v sync n/c 1 ref strobe n/c n/c n/c n/c data(b) c n/c n/c b b out n/c n/c n/c data(a) c n/c n/c n/c a a out hi-3182cj hi-3183cj 29 28 27 26 25 24 23 22 21 32 - pin cerquad 4 3 2 1 28 27 26 12 13 14 15 16 17 18 5 6 7 8 9 10 11 25 24 23 22 21 20 19 clock n/c data (b) c n/c n/c n/c b n/c data (a) n/c n/c c n/c n/c a sync n/c v v n/c n/c strobe ref 1 n/c a -v gnd +v b n/c out out hi-3182cl hi-3183cl 28 - pin ceramic lcc 16 - pin plastic small outline (esoic)** clock n/c data (b) c n/c n/c n/c b 12 13 14 15 16 17 18 5 6 7 8 9 10 11 n/c data (a) n/c n/c c n/c n/c a hi-3182pj hi-3183pj 4 3 2 1 28 27 26 sync n/c v v n/c n/c strobe ref 1 25 24 23 22 21 20 19 n/c a -v gnd +v b n/c out out 28 - pin plastic plcc holt integrated circuits 6
ordering information legend: nb - narrow body esoic - thermally enhanced small outline package (soic with built-in heat sink) wb - wide body (1) gold terminal finish is pb-free, rohs compliant. (2) only available with ?3182pj?. hi-3182, hi-3183, hi-3184, hi-3185, hi-3186, hi-3188 hi - (ceramic) 318xxx-xx hi - (plastic) 318xxx x x part package output series number description resistance fuse 3182pj 28 pin plastic j-lead plcc (28j) 37.5 ohms yes 3182ps 16 pin plastic small outline - wb esoic (16hwe) 37.5 ohms yes 3183pj 28 pin plastic j-lead plcc (28j) 13 ohms no 3183ps 16 pin plastic small outline - wb esoic (16hwe) 13 ohms no 3184ps 14 pin plastic small outline - nb esoic (14hne) 37.5 ohms yes 3185ps 14 pin plastic small outline - nb esoic (14hne) 37.5 ohms no 3186ps 14 pin plastic small outline - nb esoic (14hne) 0 ohms no 3188ps 16 pin plastic small outline - nb esoic (16hne) 0 ohms no part temperature burn number range flow in i -40c to +85c i no t -55c to +125c t no m (note 2) -55c to +125c m yes part lead number finish blank tin / lead (sn / pb) solder f 100% matte tin (pb-free, rohs compliant) part output series number resistance fuse 3182 37.5 ohms yes 3183 13 ohms no (note 1) part package lead number description finish cd 16 pin ceramic side brazed dip (16c) gold (?m? flow: solder) cj 32 pin j-lead cerquad (32u) not available with ?m? flow solder cl 28 pin ceramic leadless chip carrier (lcc) (28s) gold (?m? flow: solder) cr 16 pin cerdip (16d) not available with ?m? flow solder part temperature burn number range flow in i -40c to +85c i no t -55c to +125c t no m -55c to +125c m yes holt integrated circuits 7
revision history revision date description of change ds3182, rev. k 03/19/09 clarified the temperature ranges, and note (2) in the ordering information. hi-3182, hi-3183, hi-3184, hi-3185, hi-3186, hi-3188 holt integrated circuits 8
hi-318x package dimensions 14-pin plastic small outline (esoic) - nb (narrow body, thermally enhanced) inches (millimeters) package type: 14hne .033 .017 (.838 .43) bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) 0 to 8 detail a .0025 .0015 (.0635 .04) .0165 .003 (.419 .089) .341 .004 (8.65 .10) .0085 .001 (.220 .029) see detail a .153 .003 (3.87 .06) top view bottom view .270 (6.86) .100 (2.54) .055 .005 (1.397 .13) .050 (1.27) bsc .236 .008 (6.00 .20) typ typ 16-pin plastic small outline (esoic) - nb (narrow body, thermally enhanced) inches (millimeters) package type: 16hne bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) 0 to 8 detail a .033 .017 (.838 .43) .061 .007 (1.55 .18) .0165 .003 (.419 .09) .390 .004 (9.90 .10) .236 .008 (5.99 .20) .0086 .0015 see detail a .1525 .003 (2.87 .06) top view bottom view .10 (2.54) .050 (1.27) bsc typ .270 (6.86) typ .0025 .0015 (.0635 .04) electrically isolated heat sink pad on bottom of package. connect to any ground or power plane for optimum thermal dissipation. electrically isolated heat sink pad on bottom of package. connect to any ground or power plane for optimum thermal dissipation. holt integrated circuits 9
hi-318x package dimensions 16-pin plastic small outline (esoic) - wb (wide body, thermally enhanced) inches (millimeters) package type: 16hwe bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) .0105 .0015 (.2667 .038) .295 .004 (7.49 .10) bottom view .407 .013 (10.34 .32) .405 .008 (10.287 .20) .190 (4.83) .0165 .003 (.419 .089) top view .240 (6.10) 0 to 8 detail a .090 .010 (2.286 .254) .0025 .002 (.064 .038) .033 .017 (.838 .432) see detail a .050 (1.27) bsc typ typ electrically isolated heat sink pad on bottom of package. connect to any ground or power plane for optimum thermal dissipation. inches (millimeters) package type: 16c 16-pin ceramic side-brazed dip bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) base plane seating plane .050 .005 (1.270 .127) .295 .010 (7.493 .254) pin 1 .018 .002 (.457 .051) .010 .002 (.254 .051) .035 .010 (.889 .254) .810 (20.574) .300 .010 (7.620 .254) .100 (2.54) bsc .200 (5.080) max .125 (3.175) min max holt integrated circuits 10
hi-318x package dimensions 16-pin cerdip inches (millimeters) package type: 16d bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) .790 max (20.006 max) .200 max (5.080 max) .056 typ (1.422 typ) .288 .005 (7.315 .125) .050 max (1.27 max) .005 min (.127 min) .015 min (.381 min) 0 to 15 .010 .002 (.254 .051) .180 max (4.572 max) .310 .010 (7.874 .254) .125 min (3.175 min) .018 .003 (.457 .760) .100 bsc (2.54) 28-pin plastic plcc inches (millimeters) package type: 28j .045 x 45 .453 .003 (11.506 .076) sq. .490 .005 (12.446 .127) sq. .045 x 45 .173 .008 (4.394 .203) pin no. 1 ident pin no. 1 .410 .020 (10.414 .508) .031 .005 (.787 .127) .017 .004 (.432 .102) .050 (1.27) bsc detail a .035 .889 r .010 .001 (.254 .03) .020 (.508) min see detail a bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) holt integrated circuits 11
hi-318x package dimensions 28-pin ceramic leadless chip carrier inches (millimeters) package type: 28s bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) .451 .009 (11.455 .229) sq. .080 .020 (2.032 .508) .040 x 45 3pls (1.016 x 45 3pls) .050 .005 (1.270 .127) .025 .003 (.635 .076) pin 1 .008r .006 (.203r .152) pin 1 .050 (1.270) bsc .020 (.508) index 32-pin j-lead cerquad inches (millimeters) package type: 32u bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) .040 (1.016) .190 (4.826) .420 .012 (10.668 .305) .588 .008 (14.935 .203) .019 .003 (.483 .076) .488 .008 (12.395 .203) .450 .008 (11.430 .203) .550 .009 (13.970 .229) .520 .012 (13.208 .305) 31 32 1 2 .083 .009 (2.108 .229) .050 bsc (1.270) typ max holt integrated circuits 12

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